View CS4228-KS_1964207.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

advance product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 1999 (all rights reserved) p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.cirrus.com cs4228 24-bit, 96 khz surround sound codec features l two 24-bit a/d converters - 102 db dynamic range - 90 db thd+n l six 24-bit d/a converters - 103 db dynamic range and snr - 90 db thd+n l sample rates up to 100 khz l pop-free digital output volume controls - 90.5 db range, 0.5 db resolution (182 levels) - variable smooth ramp rate, 0.125 db steps l mute control pin for off-chip muting circuits l on-chip anti-alias and output filters l de-emphasis filters for 32, 44.1 and 48 khz description the cs4228 codec provides two analog-to-digital and six digital-to-analog delta-sigma converters, along with volume controls, in a compact +5/+3.3 v, 28-pin ssop device. combined with an iec958 (spdif) receiver (like the cs8414) and surround sound decoder (such as one of the cs492x or cs493xx families), it is ideal for use in dvd player, a/v receiver and car audio systems sup- porting multiple standards such as dolby digital ac-3, aac, dts, dolby prologic, thx, and mpeg. a flexible serial audio interface allows operation in left justified, right justified, i 2 s, or one line data modes. ordering information CS4228-KS -10 to +70 c 28-pin ssop cdb4228 evaluation board i scl/cclk sda/cdin vd aout1 lrck sclk sdin1 sdout serial audio control port digital filters analog low pass and output stage va aout2 ainl+ ainl- sdin2 mclk dgnd aout3 aout4 ainr+ ainr- left adc sdin3 mutec ad0/cs rst filt aout5 aout6 digital filters data interface vl right adc agnd with de-emphasis ds dac #1 clock manager mute control ds dac #2 ds dac #3 ds dac #4 ds dac #5 ds dac #6 digital volume digital volume digital volume digital volume digital volume digital volume dgnd agnd jul 99 ds307pp1
cs4228 2 ds307pp1 table of contents characteristics and specifications ................................................... 4 analog characteristics................................................................... 4 digital characteristics.................................................................... 6 switching characteristics ............................................................. 6 switching characteristics - control port ............................. 8 absolute maximum ratings ............................................................ 10 recommended operating conditions ........................................ 10 typical connection diagram ................................................................. 11 functional description .......................................................................... 12 overview ................................................................................................... 12 analog inputs ............................................................................................ 12 line level inputs ................................................................................ 12 high pass filter .................................................................................. 12 analog outputs ......................................................................................... 12 line level outputs ............................................................................. 12 digital volume control ....................................................................... 13 mute control ............................................................................................. 13 clock generation ...................................................................................... 14 clock source ...................................................................................... 14 synchronization .................................................................................. 14 digital interfaces ....................................................................................... 14 serial audio interface signals ............................................................ 14 serial audio interface formats ........................................................... 14 control port signals .................................................................................. 14 spi mode ........................................................................................... 16 i 2 c mode ............................................................................................ 16 control port bit definitions ........................................................................ 17 power-up/reset/power down mode ......................................................... 17 power supply, layout, and grounding ..................................................... 18 register description ................................................................................ 19 pin description............................................................................................. 24 parameter definitions ............................................................................. 28 package dimensions .................................................................................. 29 contacting cirrus logic support for a complete listing of direct sales, distributor, and sales representative contacts, visit the cirrus logic web site at: http://www.cirrus.com/corporate/contacts/ dolby, pro logic, and ac-3 are trademarks of dolby laboratories licensing corporation. preliminary product information describes products which are in production, but for which full characterization data is not yet available. advance product infor- mation describes products which are in development and subject to development changes. cirrus logic, inc. has made best effort s to ensure that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provi d ed as is without warranty of any kind (express or implied). no responsibility is assumed by cirrus logic, inc. for the use of this information, nor for inf ringements of patents or other rights of third parties. this document is the property of cirrus logic, inc. and implies no license under patents, copyrights, tradem arks, or trade secrets. no part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electron ic, mechanical, photographic, or otherwise) without the prior written consent of cirrus logic, inc. items from any cirrus logic website or disk may be printed for use by the user. however, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form o r by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of cirrus logic, inc.furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of cirrus logic, inc. the names of products of cirrus logic, inc. or ot her vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. a list of cirrus logic, inc. trade- marks and service marks can be found at http://www.cirrus.com.
cs4228 ds307pp1 3 list of figures figure 1. serial audio port master mode timing ...................................................... 7 figure 2. serial audio port slave mode timing ........................................................ 7 figure 3. spi control port timing ............................................................................. 8 figure 4. i 2 c control port timing .............................................................................. 9 figure 5. recommended connection diagram ....................................................... 11 figure 6. optional line input buffer ........................................................................ 12 figure 7. passive output filter with mute ............................................................... 13 figure 8. butterworth output filter with mute .......................................................... 13 figure 9. right justified serial audio formats ........................................................ 15 figure 10.i 2 s serial audio formats .......................................................................... 15 figure 11.left justified serial audio formats .......................................................... 15 figure 12.one line data serial audio format ......................................................... 16 figure 13.control port timing, spi mode ................................................................ 17 figure 14.control port timing, i 2 c mode ................................................................. 17
cs4228 4 ds307pp1 characteristics and specifications analog characteristics (unless otherwise specified t a = 25c; va = +5v, vd = vl = +3.3v; full scale input sine wave, 1khz; fs = 44.1 khz brm, 96 khz hrm; measurement bandwidth is 20 hz to 20 khz; local components as shown in "recommended connection diagram"; spi control mode, left justified serial for- mat, mclk = 256 fs brm, 128 fs hrm, sclk = 64 fs) notes: 1. referenced to typical full-scale differential input voltage (2 vrms). 2. filter characteristics scale with output sample rate. 3. the analog modulator samples the input at 5.6448 mhz for an output sample rate of 44.1 khz. there is no rejection of input signals which are multiples of the sampling frequency (n 5.6448 mhz 20.0 khz where n = 0,1,2,3...). 4. group delay for fs = 44.1 khz, t gd = 15/44.1 khz = 340 m s. fs = sample rate. specifications are subject to change without notice base rate mode high rate mode parameter symbol min typ max min typ max units analog input characteristics - minimum gain setting (0 db) differential input; unless otherwise specified. adc resolution stereo audio channels 16 - 24 16 24 bits total harmonic distortion thd - 0.003 - - 0.003 - % dynamic range (a weighted) (unweighted) tbd - 102 99 - - tbd tbd 102 99 - - db db total harmonic distortion + noise -1db (note 1) thd+n - -90 tbd - -90 tbd db interchannel isolation -90- -90- db interchannel gain mismatch - 0.1 - - 0.1 - db offset error (with high pass filter) --0--0lsb full scale input voltage (differential): 5.66 5.66 vp-p gain drift - 100 - - 100 - ppm/c input resistance 10--10--k w input capacitance - - 15 15 pf a/d decimation filter characteristics passband (note 2) 0.02 - 20.0 0.02 - 40 khz passband ripple - - 0.01 - - 0.05 db stopband (note 2) 27.56 - 5617 66.53 - 5578 khz stopband attenuation (note 3) 80--45--db group delay (note 4) t gd - 15/fs - - 15/fs - s group delay variation vs. frequency d t gd --0--0 m s high pass filter characteristics frequency response: -3 db (note 2) -0.13 db - - 3.4 20 - - - - 3.4 20 - - hz hz phase deviation @ 20 hz (note 2) -10- -10-degree passband ripple --0--0db
cs4228 ds307pp1 5 analog characteristics (continued) notes: 5. the passband and stopband edges scale with frequency. for input word rates, fs, other than 44.1 khz, the 0.01 db passband edge is 0.4535fs and the stopband edge is 0.5465fs. 6. digital filter characteristics. 7. measurement bandwidth is 10 hz to 3 fs. specifications are subject to change without notice base rate mode high rate mode parameter symbol min typ max min typ max units analog output characteristics - minimum attenuation, 10 k w , 100 pf load; unless otherwise specified. dac resolution 16 - 24 16 24 bits signal-to-noise/idle channel noise (dac muted, a weighted) tbd 103 - tbd 103 - db dynamic range (dac not muted, a weighted) (dac not muted, unweighted) tbd - 103 100 - - - - 103 100 - - db db total harmonic distortion thd - 0.003 - - 0.003 - % total harmonic distortion + noise thd+n - -90 tbd - -90 - db interchannel isolation -90- -90- db interchannel gain mismatch - 0.1 - - 0.1 - db attenuation step size (all outputs) tbd 0.5 tbd tbd 0.5 tbd db programmable output attenuation span tbd -90.5 - tbd -90.5 - db offset voltage -10- -10- mv full scale output voltage tbd 1.3 tbd - 1.3 - vrms gain drift - 100 - - 100 - ppm/c analog output load minimum load resistance: maximum load capacitance: - - 10 100 - - - - 10 100 - - k w pf combined digital and analog filter characteristics frequency response 10 hz to 20 khz 0.1 0.1 db deviation from linear phase - 0.5 - - 0.5 - degrees passband: to 0.01 db corner (notes 5, 6) 0 - 20.0 0 - 40 khz passband ripple (note 6) - - 0.01 - - 0.01 db stopband (notes 5, 6) 24.1 - - 56 - - khz stopband attenuation (notes 4, 7) 70--65--db group delay (fs = input word rate) tgd - 16/fs - - 16/fs - s analog loopback performance signal-to-noise ratio (ccir-2k weighted, -20 db fs input) ccir-2k - tbd - - tbd - db
cs4228 6 ds307pp1 analog characteristics (continued) digital characteristics unless otherwise specified (t a = 25 c; vd = vl = +3.3v; va =+ 5v) switching characteristics (t a = 25c; vd = vl = +3.3v, va = +5v, outputs loaded with 30 pf) power supply symbol min typ max min typ max units power supply current operating va = 5v, vd = vl = 3.3v va vl vd power down va vl vd - - - - - - 25 2 42 tbd 2 0.1 tbd tbd tbd tbd tbd tbd - - - - - - 25 2 48 tbd 2 0.1 tbd tbd tbd tbd tbd tbd ma ma ma ma ma ma power supply rejection (1 khz, 10 mv rms ) - 50 - 50 db parameter symbol min typ max units high-level input voltage v ih 0.7xvl - - v low-level input voltage v il -0.3xvlv high-level output voltage at i 0 = -2.0 ma v oh vl - 1.0 - - v low-level output voltage at i 0 = 2.0 ma v ol --0.4v input leakage current (digital inputs) --10 m a output leakage current (high-impedance digital outputs) --10 m a parameter symbol min typ max units audio adc's & dac's sample rate brm hrm fs 30 60 - - 50 100 khz khz mclk frequency 3.84 - 25.6 mhz mclk duty cycle brm mclk =128, 384 fs mclk = 256, 512 fs hrm mclk = 64, 192 fs mclk = 128, 256 fs tbd 40 tbd 40 50 50 - tbd 60 tbd 60 % % % % mclk jitter tolerance -500-ps
cs4228 ds307pp1 7 switching characteristics (continued) notes: 8. after powering up the cs4228, rst should be held low until the power supplies and clocks are settled. parameter symbol typ max units rst low time (note 8) 1- -ms sclk falling edge to sdout output valid (dsck=0) t dpd -tbdns lrck edge to msb valid t lrpd -tbdns sdin setup time before sclk rising edge t ds -tbdns sdin hold time after sclk rising edge t dh -tbdns master mode sclk falling to lrck edge t mslr + 10 - ns sclk duty cycle 50 - % slave mode sclk period t sckw --ns sclk high time t sckh tbd - - ns sclk low time t sckl tbd - - ns sclk rising to lrck edge (dsck=0) t lrckd tbd - - ns lrck edge to sclk rising (dsck=0) t lrcks tbd - - ns figure 1. serial audio port master mode timing t mslr sclk* (output) lrck (output) sdout sckh sckl sckw t t t msb msb-1 *sclk shown for dsck = 0. sclk inverted for dsck = 1. t dpd sdout lrck (input) sclk* (input) sdin1 sdin2 sdin3 dh t ds t lrpd t lrcks t lrckd t figure 2. serial audio port slave mode timing
cs4228 8 ds307pp1 switching characteristics - control port (ta = 25c, vd = vl = +3.3v, va = +5v; inputs: logic 0 = dgnd, logic 1 = vl+, c l = 30 pf) notes: 9. data must be held for sufficient time to bridge the transition time of cclk. 10. for f sck < 1 mhz parameter symbol min max units spi mode (sdout > 47k w to gnd) cclk clock frequency f sck -6mhz cs high time between transmissions t csh 1.0 m s cs falling to cclk edge t css 20 ns cclk low time t scl 66 ns cclk high time t sch 66 ns cdin to cclk rising setup time t dsu 40 ns cclk rising to data hold time (note 9) t dh 15 ns rise time of cclk and cdin (note 10) t r2 100 ns fall time of cclk and cdin (note 10) t f2 100 ns t r2 t f2 t dsu t dh t sch t scl cs cclk cdin t css t csh figure 3. spi control port timing
cs4228 ds307pp1 9 switching characteristics - control port (t a = 25c; vd = vl = +3.3v, va = +5v; inputs: logic 0 = dgnd, logic 1 = vl, c l = 30 pf) notes: 11. use of the i 2 c bus interface requires a license from philips. i 2 c is a registered trademark of philips semiconductors. 12. data must be held for sufficient time to bridge the 300 ns transition time of scl. parameter symbol min max units i 2 c ? mode (sdout < 47k w to ground) (note 11) scl clock frequency f scl -100khz bus free time between transmissions t buf 4.7 m s start condition hold time (prior to first clock pulse) t hdst 4.0 m s clock low time t low 4.7 m s clock high time t high 4.0 m s setup time for repeated start condition t sust 4.7 m s sda hold time from scl falling (note 12) t hdd 0 m s sda setup time to scl rising t sud 250 ns rise time of both sda and scl lines t r 1 m s fall time of both sda and scl lines t f 300 ns setup time for stop condition t susp 4.7 m s t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp stop start start stop repeated sda scl figure 4. i 2 c control port timing
cs4228 10 ds307pp1 absolute maximum ratings (agnd, dgnd = 0 v, all voltages with respect to 0 v.) notes: 13. any pin except supplies. transient currents of up to 100 ma on the analog input pins will not cause scr latch-up. 14. the maximum over or under voltage is limited by the input current. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (agnd, dgnd = 0 v, all voltages with respect to 0 v.) parameter symbol min typ max units power supplies digital analog interface vd va vl -0.3 -0.3 -0.3 - - - 6.0 6.0 6.0 v v v input current (note 13) --10ma analog input voltage (note 14) -0.7 - va + 0.7 v digital input voltage (note 14) -0.7 - vl + 0.7 v ambient temperature (power applied) -55 - +125 c storage temperature -65 - +150 c parameter symbol min typ max units power supplies digital analog interface vd va vl tbd 4.75 2.7 3.3 5.0 5.0 tbd 5.25 5.25 v v v operating ambient temperature t a -10 25 70 c
cs4228 ds307pp1 11 typical connection diagram +5v supply + 1 m f 0.1 m f + 1 m f 0.1 m f va vd agnd dgnd mclk external clock input all unused inputs should be tied to 0v. aout1 aout2 aout3 aout4 aout5 aout6 filt 150 w ainl- ainl+ ainr- ainr+ cs4228 analog filter from analog input stage mutec +3.3v or 5 v supply vl + 1 m f 0.1 m f 10 7 22 15 28 27 26 25 24 23 9 8 21 18 19 17 16 10 m f ferrite bead analog filter analog filter analog filter analog filter analog filter 2 * required for i c control port mode only vl 150 w 2.2 nf 2.2 nf +3.3v supply ferrite bead ferrite bead digital audio peripheral or dsp sdin1 sdin2 sdin3 sdout lrck sclk 50 w 50 w 33 k* 4 1 2 3 5 6 50 w microcontroller scl/cclk ad0/cs rst 14 13 11 sda/cdin 12 2.2 k* vl 22 m f 22 m f + + + 100 m f 100 m f + + 0.1 m f 20 0.1 m f figure 5. recommended connection diagram
cs4228 12 ds307pp1 functional description overview the cs4228 is a 24-bit audio codec comprised of 2 analog-to-digital converters (adc) and 6 digital- to-analog converters (dac), all implemented us- ing single-bit delta-sigma techniques. other func- tions integrated with the codec include independent digital volume controls for each dac, digital dac de-emphasis filters, adc high-pass filters, an on- chip voltage reference, and a flexible serial audio interface. all functions are configured through a serial control port operable in spi and i 2 c compat- ible modes. figure 5 shows the recommended con- nections for the cs4228. analog inputs line level inputs ainr+, ainr-, ainl+, and ainl- are the line level analog inputs (see figure 5). these pins are internally biased to a dc operating voltage of ap- proximately 2.3 vdc. ac coupling the inputs pre- serves this bias and minimizes signal distortion. figure 5 shows operation with a single-ended input source. this source may be supplied to either the positive or negative input as long as the unused in- put is connected to ground through capacitors as shown. when operated with single-ended inputs, distortion will increase at input levels higher than -1 dbfs. figure 6 shows an example of a differen- tial input circuit. muting of the stereo adc is possible through the adc control byte. the adc output data is in 2s complement binary format. for inputs above positive full scale or be- low negative full scale, the adc will output 7fffffh or 800000h, respectively. high pass filter digital high pass filters in the signal path after the adcs remove any dc offsets present on the analog inputs. this helps to prevent audible "clicks" when switching the audio in devices downstream from the adcs. the high pass filter response, given in high pass filter characteristics on page 4, scales linearly with sample rate. thus, for high rate mode, the -3 db frequency at a 96 khz sample rate will be equal to 96/44.1 times that at a sample rate of 44.1 khz. the high pass filters can be disabled by setting the hpf bit in the adc control register. when assert- ed, any dc present at the analog inputs will be rep- resented in the adc outputs. the high pass filter may also be frozen using the hpfz bit in the adc control register. in this condition, it will re- member the dc offset present at the adc inputs at the moment the hpfz bit was asserted, and will continue to remove this dc level from the adc outputs. this is useful in cases where it is desirable to eliminate a fixed dc offset while still maintain- ing full frequency response down to dc. analog outputs line level outputs the cs4228 contains on-chip buffer amplifiers ca- pable of producing line level outputs. these ampli- fiers are biased to a quiescent dc level of approximately 2.3 v. this bias, as well as varia- tions in offset voltage, are removed using off-chip ac load coupling. + - 0.1 m f 10 m f 10 k + - 4.7 k 10 k ain - 10 m f va + ain + 2.2 nf 150 150 10 k 10 k ~ 8.5 k signal + figure 6. optional line input buffer
cs4228 ds307pp1 13 high frequency noise beyond the audio passband, resulting from the delta-sigma conversion process produces high frequency noise beyond the audio passband, most of which is removed by the on-chip analog filters. the remaining out-of-band noise can be attenuated using an off-chip low pass filter. for most applications, a simple passive filter as show in figure 7 can be used. note that this circuit also serves to block the dc present at the outputs. fig- ure 8 gives an example of a filter which can be used in applications where greater out of band attenua- tion is desired. the 2-pole butterworth filter has a -3 db frequency of 50 khz, a passband attenuation of 0.1 db at 20 khz providing optimal out-of-band filtering for sample rates from 44.1 khz to 96 khz. the filter has and a gain of 1.56 providing a 2 vrms output signal. digital volume control each dacs output level is controlled via the dig- ital volume control register operating over the range of 0 to 90.5 db attenuation with 0.5 db reso- lution. volume control changes do not occur in- stantaneously. instead they ramp in increments of 0.125 db at a variable rate controlled by the rmp1:0 bits in the digital volume control regis- ter. each output can be independently muted via mute control bits mut6-1 in the dac mute1 control register. when asserted, mut attenuates the corre- sponding dac to its maximum value (90.5 db). when mut is deasserted, the corresponding dac returns to the attenuation level set in the digital volume control register. the attenuation is ramped up and down at the rate specified by the rmp1:0 bits. to achieve complete digital attenutation of an in- coming signal, hard mute controls are provided. when asserted, hard mute will send zero data to a corresponding pair of dacs. hard mute is not ramped, so it should only be asserted after setting the two corresponding mut bits to prevent high frequency noise from appearing on the dac out- puts. hard mute is controlled by the hmute56/34/12 bits in the dac mute2 control register. mute control the mute control pin is typically connected to an external mute control circuit as shown in figure 7 and figure 8. mute control is asserted during pow- er up, power down, and when serial port clock er- rors are present. the pin can also be controlled by the user via the control port, or automatically as- serted when zero data is present on all six dac in- puts. to prevent large transients on the output, it is desirable to mute the dac outputs before the mute control pin is asserted. please see the mutec pin in the pin descriptions section for more informa- tion. 560 2sc2878 2.2 k mun2iiit1 10 k mutec line out mutedrv 10 k + 22 m f 100 k aout figure 7. passive output filter with mute c=142 m f c f s _ 3.16 k + a out 3.16 k mc33078 1nf gnd 1nf 10 m f + mute drv line out mute 5 6 7 100 pf 3.16 k 1.78 k +12 -12 _ 3.16 k + a out 3.16 k mc33078 1nf gnd 1nf 10 m f + mute drv line out mute 5 6 7 100 pf 3.16 k 1.78 k +12 -12 figure 8. butterworth output filter with mute
cs4228 14 ds307pp1 clock generation the master clock, mclk, is supplied to the cs4228 from an external clock source. if mclk stops for 10s, the cs4228 will enter power down mode in which the supply current is reduced as specified under power supply on page 6. in all modes it is required that the number of mclk pe- riods per sclk and lrck period be constant. clock source the cs4228 internal logic requires an external master clock, mclk, that operates at multiples of the sample rate frequency, fs. the mclk/fs ratio is determined by the ci1:0 bits in the codec clock mode register. synchronization the serial port is internally synchronized with mclk. if from one lrck cycle to the next, the number of mclk cycles per lrck cycle changes by more than 32, the cs4228 will undergo an inter- nal reset of its data paths in an attempt to resyn- chronize. consequently, it is advisable to mute the dacs when changing from one clock source to an- other to avoid the output of undesirable audio sig- nals as the device resynchronizes. digital interfaces serial audio interface signals the serial audio data is presented in 2's comple- ment binary form with the msb first in all formats. the serial interface clock, sclk, is used for both transmitting and receiving audio data. sclk can be generated by the cs4228 (master mode) or it can be input from an external source (slave mode). mode selection is made with the dms1:0 bits in the serial port mode register. the number of sclk cycles in one sample period can be set using the dck1:0 bits as detailed in the serial port mode register. the left/right clock (lrck) is used to indicate left and right data frames and the start of a new sample period. it may be an output of the cs4228 (master mode), or it may be generated by an exter- nal source (slave mode). the frequency of lrck is the same as the system sample rate, fs. sdin1, sdin2, and sdin3 are the data input pins. sdout, the data output pin, carries data from the two 24-bit adc's. the serial audio port may also be operated in one line data mode in which all 6 channels of dac data is input on sdin1 and the stereo adc data is output on sdout. table 1 out- lines the serial port input to dac channel alloca- tions. serial audio interface formats the digital audio port supports 6 formats, shown in figures 9, 10, 11 and 12. these formats are selected using the ddf2:0 bits in the serial port mode reg- ister. in one line data mode, all 6 dac channels are in- put on sdin1. one line data mode is only avail- able in brm. see figure 12 for channel allocations. control port signals internal registers are accessed through the control port. the control port may be operated asynchro- nously with respect to audio sample rate. however, to avoid potential interference problems, the con- trol port pins should remain static if no register ac- cess is required. dac inputs sdin1 left channel right channel single line dac #1 dac #2 all 6 dac channels sdin2 left channel right channel dac #3 dac #4 sdin3 left channel right channel dac #5 dac #6 table 1. serial audio port input channel allocations
cs4228 ds307pp1 15 lrck sclk left channel right channel sdin1/2/3 sdout 6543210 987 15 14 13 12 11 10 6543210 987 15 14 13 12 11 10 figure 9. right justified serial audio formats right justified mode, data valid on rising edge of sclk bits/sample sclk rate(s) notes 16 32, 48, 64, 128 fs 48 fs slave only 20 48, 64, 128 fs 48 fs slave only 24 48, 64, 128 fs 48 fs slave only figure 11. i 2 s serial audio formats i2s mode, data valid on rising edge of sclk bits/sample sclk rate(s) notes 16 32, 48, 64, 128 fs 48 fs slave only 18 to 24 48, 64, 128 fs 48 fs slave only lrck sclk left channel right channel sdin1/2/3 sdout +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 lrck sclk left channel right channel sdin1/2/3 sdout +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 figure 10. left justified serial audio formats left justified mode, data valid on rising edge of sclk bits/sample sclk rate(s) notes 16 32, 48, 64, 128 fs 48 fs slave only 18 to 24 48, 64, 128 fs 48 fs slave only
cs4228 16 ds307pp1 the control port has 2 operating modes: spi and i 2 c compatible. in both modes the cs4228 oper- ates as a slave device. mode selection is deter- mined by the state of the sdout pin when rst transitions from low to high: high for spi, low for i 2 c. sdout is internally pulled high to vl. a re- sistive load from sdout to dgnd of less than 47 k w will enable i 2 c mode after a reset. spi mode in spi mode, cs is the cs4228 chip select signal, cclk is the control port bit clock input, and cdin is the input data line. there is no data output line, therefore all registers are write-only in spi mode. data is clocked in on the rising edge of cclk. figure 13 shows the operation of the control port in spi mode. the first 7 bits on cdin, after cs goes low, form the chip address (0010000). the eighth bit is a read/write indicator (r/w ), which should be low to write. the next 8 bits set the memory ad- dress pointer (map) which is the address of the register that is to be written. the following bytes contain the data which will be placed into the reg- isters designated by the map. the cs4228 has a map auto increment capability, enabled by the incr bit in the map register. if incr is zero, then the map will stay constant for successive reads or writes. if incr is 1, then map will increment after each byte is read or written, al- lowing block reads or writes of successive regis- ters. i 2 c mode in i 2 c mode, sda is a bidirectional data line. data is clocked into and out of the port by the scl clock. the signal timing is shown in figure 14. the ad0 pin forms the lsb of the chip address. the upper 6 bits of the 7 bit address field must be 001000. to communicate with a cs4228, the lsb of the chip address field, which is the first byte sent to the cs4228 after a start condition, should match the setting of the ad0 pin. the eighth bit of the address bit is the r/w bit (high for a read, low for a write). when writing, the next byte is the memory ad- dress pointer (map) which selects the register to be read or written. if the operation is a read, the contents of the register pointed to by the map will be output. setting the auto increment bit in the lrck sclk sdin1/2/3 lsb msb 20 clks 64 clks 64 clks lsb msb lsb msb lsb msb lsb msb lsb msb msb dac1 dac3 dac5 dac2 dac4 dac6 20 clks 20 clks 20 clks 20 clks 20 clks 20 clks adcl adcr 20 clks sdout left channel right channel figure 12. one line data serial audio format one line data mode, data valid on rising edge of sclk bits/sample sclk rate(s) notes 20 128 fs 6 inputs, 2 outputs, brm only
cs4228 ds307pp1 17 map allows successive reads or writes of consecu- tive registers. each byte is separated by an ac- knowledge bit. control port bit definitions all registers are read/write, except the chip status register which is read-only. for more detailed in- formation, see the bit definition tables starting on page 19. power-up/reset/power down mode upon power up, the user should hold rst = 0 until the power supplies and clocks stabilize. in this state, the control registers are reset to their default settings, and the device remains in a low power mode in which the control port is inactive. the part may be held in a low power reset state by clearing the digpdn bit in the chip control register. in this state, the digital portions of the codec are in re- set, but the control port is active and the desired register settings can be loaded. normal operation is achieved by setting the digpdn bit to 1, at which time the codec powers up and normal operation begins. the cs4228 will enter a stand-by mode if the mas- ter clock source stops for approximately 10 m s or if the number of mclk cycles per lrck period var- ies by more than 32. should this occur, the control registers retain their settings. map msb lsb data byte 1 byte n r/w r/w map = memory address pointer address chip address chip cdin cclk cs 0010000 0010000 figure 13. control port timing, spi mode sda scl ad 0 r/w start ack ack ack stop note 1: if operation is a write, this byte contains the memory address pointer, map. note 1 001000 d7:0 d7:0 figure 14. control port timing, i 2 c mode
cs4228 18 ds307pp1 the cs4228 will mute the analog outputs, assert the mutec pin and enter the power down mode if the supply drops below approximately 4 volts. power supply, layout, and grounding the cs4228 requires careful attention to power supply and grounding details. va is normally sup- plied from the system analog supply. vd is from a 3.3vdc supply, and vl should be from the supply used for the devices digitally interfacing with the cs4228. the power up sequence of these three supply pins is not important. agnd and dgnd pins should both be tied to a solid ground plane surrounding the cs4228. if the system analog and digital ground planes are sepa- rate, they should be connected at a point near where the supply currents enter the board. a solid ground plane underneath the part is recommended. decoupling capacitors should be mounted in such a way as to minimize the circuit path length from the cs4228 supply pin, through the capacitor, to the applicable cs4228 agnd or dgnd pin. the small value ceramic capacitors should be closest to the part. in some cases, ferrite beads in the vl, vd and va supply lines, and low-value resistances (~ 50 w) in series with the lrck, sclk, and sd- out lines can help reduce coupling of digital sig- nals into the analog. the capacitor on the filt pin should be as close to the cs4228 as possible. see crystal's layout appli- cations note, and the cdb4228 evaluation board data sheet for recommended layout of the decou- pling components.
cs4228 ds307pp1 19 register description all registers are read/write except for chip status, which is read only. see the following bit definition tables for bit assignment information. the default bit state after power-up sequence or reset is listed underneath the bit definition for that field. default values are also marked with an asterick. memory address pointer (map) - not a register incr memory address pointer auto increment control 0 - map is not incremented automatically. *1 - internal map is automatically incremented after each read or write. map4:0 memory address pointer (map). sets the register address that will be read or written by the con- trol port. codec clock mode address 0x01 hrm sets the sample rate mode for the adcs and dacs *0 - base rate mode (brm) supports sample rates up to 50khz 1 - high rate mode (hrm) supports sample rates up to 100 khz. typically used for 96 khz sample rate. ci1:0 specifies the ratio of mclk to the sample rate of the adcs and dacs (fs) 76543210 incr reserved map4 map3 map2 map1 map0 10000001 76543210 hrm reserved ci1 ci0 reserved 00000100 ci1:0 brm (fs) hrm (fs) 0 128 64 *1 256 128 2384192 3512256
cs4228 20 ds307pp1 chip control address 0x02 digpdn power down the digital portions of the codec 0 - digital power down. *1 - normal operation adcpdn power down the analog section of the adc *0 - normal 1 - adc power down. dacpdn12 power down the analog section of dac 1&2 *0 - normal 1 - power down dac 1&2. dacpdn34 power down the analog section of dac 3&4 *0 - normal 1 - power down dac 3&4. dacpdn56 power down the analog section of dac 5&6 *0 - normal 1 - power down dac 5&6. adc control address 0x03 mutl, mutr adc left and right channel mute control *0 - normal 1 - selected adc output muted hpf adc dc offset removal. see high pass filter on page 12 for more information *0 - enabled 1 - disabled hpfz adc dc offset averaging freeze. see high pass filter on page 12 for more information *0 - normal. the dc offset average is dynamically calculated and subtracted from incoming adc data. 1 - freeze. the dc offset average is frozen at the current value and subtracted from incoming adc data. allows passthru of dc information. 7 6543210 digpdn reserved adcpdn dacpdn56 dacpdn34 dacpdn12 reserved 1 0000000 76543210 mutl mutr hpf hpfz reserved 00000000
cs4228 ds307pp1 21 dac mute1 control address 0x04 mut6 - mut1 mute control for dac6 - dac1 respectively. when asserted, the corresponding dac is digitally attenuated to its maximum value (90.5 db). when deasserted, the corresponding dac attenu- tation value returns to the value stored in the corresponding digital volume control register. the attenuation value is ramped up and down at the rate specified by rmp1:0. 0 - normal output level *1 - selected dac output fully attenuated. rmp1:0 attenuation ramp rate. *0 - 0.5db change per 4 lrcks 1 - 0.5db change per 8 lrcks 2 - 0.5db change per 16 lrcks 3 - 0.5db change per 32 lrcks dac mute2 control address 0x05 mutec controls the mutec pin *0 - normal operation 1 - mutec pin asserted low mutcz automatically asserts the mutec pin on consecutive zeros. when enabled, 512 consecutive zeros on all six dac inputs will cause the mutec pin to be asserted low. a single non-zero value on any dac input will cause the mutec pin to deassert. *0 - disabled 1 - enabled hmute56/34/12 hard mute the corresponding dac pair. when asserted, zero data is sent to the corresponding dac pair causing an instantaneous mute. to prevent high frequency transients on the outputs, a dac pair should be fully attenuated by asserting the corresponding mut6-mut1 bits in the dac mute control register or by writing 0xff to the corresponding digital volume control reg- isters before asserting hmute. *0 - normal operation 1 - dac pair is muted 76543210 mut6 mut5 mut4 mut3 mut2 mut1 rmp1 rmp0 11111100 76543210 mutec mutcz reserved hmute56 hmute34 hmute12 reserved 00000000
cs4228 22 ds307pp1 dac de-emphasis control address 0x06 dems1:0 selects the dac de-emphasis response curve. 0 - reserved 1 - de-emphasis for 48 khz *2 - de-emphasis for 44.1 khz 3 - de-emphasis for 32 khz dem6 - dem1 de-emphasis control for dac6 - dac1 respectively *0 - de-emphasis off 1 - de-emphasis on digital volume control addresses 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c vol6 - vol1 address 0x0c - 0x07 sets the attenuation level for dac 6 - dac1 respectively. the attenutation level is ramped up and down at the rate specified by rmp1:0 in the dac volume control setup register. 0 - 181 represents 0 to 90.5 db of attenuation in 0.5 db steps. 76543210 dems1 dems0 dem6 dem5 dem4 dem3 dem2 dem1 10000000 76543210 voln 00000000
cs4228 ds307pp1 23 serial port mode address 0x0d dck1:0 sets the number of serial clocks (sclk) per fs period (lrclk) dms1:0 sets the master/slave mode of the serial audio port *0 - slave (external lrclk, sclk) 1 - reserved 2 - reserved 3 - master (no 48 fs sclk in brm, no 24 fs sclk in hrm) ddf2:0 serial port data format 0 - right justified, 24-bit 1 - right justified, 20-bit 2 - right justified, 16-bit 3 - left justified, maximum 24-bit *4 - i 2 s compatible, maximum 24-bit 5 - one-line data mode, available in brm only 6 - reserved 7 - reserved chip status address 0x0e clkerr clocking system status, read only 0 - no error 1 - no mclk is present, or a request for clock change is in progress adcovl adc overflow bit, read only 0 - no overflow 1 - adc overflow has occurred 76543210 dck1 dck0 dms1 dms0 reserved ddf2 ddf1 dff0 10000100 dck1:0 brm (fs) hrm (fs) 0 32 (1) 16 (3) 1 48 (2) 24 (4) 2 *64 32 (1) 3 128 64 notes: 1. all formats will default to 16 bits 2. external slave mode only 3. only valid for left justified and i 2 s modes 4. only valid for left justified and i 2 s, external slave mode only 7 6543210 clkerr adcovl reserved xx000000
cs4228 24 ds307pp1 pin description serial audio data in - sdin3, sdin2, sdin1 pin 1, 2, 3, input function: two's complement msb-first serial audio data is input on this pin. the data is clocked into sdin1, sdin2, sdin3 via the serial clock and the channel is determined by the left/right clock. the required relationship between the left/right clock, serial clock and serial data is defined by the serial mode register. the op- tions are detailed in figures 9, 10, 11 and 12. serial audio data out - sdout pin 4, output function: two's complement msb-first serial data is output on this pin. the data is clocked out of sdout via the serial clock and the channel is determined by the left/right clock. the required relationship between the left/right clock, serial clock and serial data is defined by the serial mode register. the options are de- tailed in figures 9, 10, 11 and 12. the state of the sdout pin during reset is used to set the control port mode (i2c or spi). when rst is low, sdout is configured as an input, and the rising edge of rst latches the state of the pin. a weak internal pull up is present such that a resistive load less than 47 k w will pull the pin low, and the control port mode is i2c. when the resistive load on sdout is greater than 47 k w during reset, the control port mode is spi. serial audio data in 3 sdin3 aout6 analog output 6 serial audio data in 2 sdin2 aout5 analog output 5 serial audio data in 1 sdin1 aout4 analog output 4 serial audio data out sdout aout3 analog output 3 serial clock sclk aout2 analog output 2 left/right clock lrck aout1 analog output 1 digital ground dgnd agnd analog ground digital power vd va analog power digital interface power vl ainl+ left channel analog input+ master clock mclk ainl- left channel analog input- scl/cclk scl/cclk filt internal voltage filter sda/cdin sda/cdin ainr - right channel analog input- ad0/cs ad0/cs ainr + right channel analog input+ reset rst mutec mute control 1 2 3 4 5 6 7 8 9 10 11 12 5 1 2 6 24 23 22 21 20 19 18 17 16 15 14 13 25 26 27 28
cs4228 ds307pp1 25 serial clock sclk pin 5, bidirectional function: clocks serial data into the sdin1, sdin2, and sdin3 pins, and out of the sdout pin. the pin is an output in master mode, and an input in slave mode. in master mode, sclk is configured as an output. mclk is divided internally to generate sclk at the desired multiple of the sample rate. in slave mode, sclk is configured as an input. the serial clock can be provided externally, or the pin can be grounded and the serial clock derived internally from mclk. the required relationship between the left/right clock, serial clock and serial audio data is defined by the serial port mode register. the options are detailed in figures 9, 10, 11 and 12. left/right clock lrck pin 6, bidirectional function: the left/right clock determines which channel is currently being input or output on the serial audio data output, sdout. the frequency of the left/right clock must be at the output sample rate, fs. in master mode, lrck is an output, in slave mode, lrck is an input whose frequency must be equal to fs and synchronous to the master clock. audio samples in left/right pairs represent simultaneously sampled analog inputs whereas right/left pairs will exhibit a one sample period difference. the required relationship between the left/right clock, serial clock and serial data is defined by the serial port mode register. the options are detailed in figures 9, 10, 11 and 12. digital ground - dgnd pin 7, inputs function: digital ground reference. digital power - vd pin 8, input function: digital power supply. typically 3.3 vdc. digital interface power - vl pin 9, input function: digital interface power supply. typically 3.3 or 5.0 vdc. all digital output voltages and input thresholds scale with vl.
cs4228 26 ds307pp1 master clock - mclk pin 10, input function: the master clock frequency must be either 128x, 256x, 384x or 512x the input sample rate in base rate mode (brm) and either 64x, 128x, 192x, or 256x the input sample rate in high rate mode (hrm). table 2 illustrates several standard audio sample rates and the required master clock frequencies. the mclk/fs ration is set by the ci1:0 bits in the codec clock mode register serial control interface clock - scl/cclk pin 11, input function: clocks serial control data into or out of sda/cdin. serial control data i/o - sda/cdin pin 12, bidirectional/input function: in i 2 c mode, sda is a bidirectional control port data line. a pull up resistor must be provided for proper open drain output operation. in spi mode, cdin is the control port data input line. the state of the sdout pin during reset is used to set the control port mode. address bit 0 / chip select - ado/cs pin 13, input function: in i 2 c mode, ad0 is the lsb of the chip address. in spi mode, cs is used as a enable for the control port interface. reset - rst pin 14, input function: when low, the device enters a low power mode and all internal registers are reset to the default settings, including the control port. the control port can not be accessed when reset is low. when high, the control port and the codec become operational. sample rate (khz) mclk (mhz) hrm brm 64x 128x 192x 256x 128x 256x 384x 512x 32----4.09608.192012.288016.3840 44.1----5.644811.289616.934422.5792 48----6.144012.288018.432024.5760 64 4.0960 8.1920 12.2880 16.3840 - - - - 88.2 5.6448 11.2896 16.9344 22.5792 - - - - 96 6.1440 12.2880 18.4320 24.5760 - - - - table 2. common master clock frequencies
cs4228 ds307pp1 27 mute control - mutec pin 15, output function: the mute control pin goes low during the following conditions: power-up initialization, power-down, reset, no master clock present, or if the master clock to left/right clock frequency ratio is incorrect. the mute con- trol pin can also be user controlled by the mutec bit in the dac mute2 control register. mute control can be automatically asserted when 512 consecutive zeros are detected on all six dac inputs, and automat- ically deasserted when a single non-zero value is sent to any of the six dacs. the mute on zero function is controlled by the mutcz bit in the dac mute2 control register. the mutec pin is intended to be used as a control for an external mute circuit to achieve a very low noise floor during periods when no audio is present on the dac outputs, and to prevent the clicks and pops that can occur in any single supply sys- tem. use of the mute control pin is not mandatory but recommended. differential analog inputs ainr+, ainr- and ainl+, ainl- pins 16, 17 and 19, 20, inputs function: the analog signal inputs are presented deferentially to the modulators via the ainr+/- and ainl+/- pins. the + and - input signals are 180 out of phase resulting in a nominal differential input voltage of twice the input pin voltage. these pins are biased to the internal reference voltage of approximately 2.3 v. a pas- sive anti-aliasing filter is required for best performance, as shown in figure 5. the inputs can be driven at -1db fs single-ended if the unused input is connected to ground through a large value capacitor. a single ended to differential converter circuit can also be used for slightly better performance. internal voltage filter - filt pin 18, output function: filter for internal circuits. an external capacitor is required from filt to analog ground, as shown in figure 5. filt is not intended to supply external current. filt+ has a typical source impedance of 250 k w and any current drawn from this pin will alter device performance. care should be taken during board layout to keep dynamic signal traces away from this pin. analog power - va pin 21, input function: power for the analog and reference circuits. typically 5.0 vdc. analog ground - agnd pin 22, input function: analog ground reference. analog output - aout1, aout2, aout3, aout4, aout5 and aout6 pins 23, 24, 25, 26, 27, 28, outputs function: analog outputs from the dacs. the full scale analog output level is specified in the analog characteristics specifications table. the amplitude of the outputs is controlled by the digital volume control registers vol6 - vol1.
cs4228 28 ds307pp1 parameter definitions dynamic range the ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is then added to the resulting measurement to refer the measurement to full scale. this technique ensures that the distortion components are below the noise level and do not effect the measurement. this measurement technique has been accepted by the audio engineering society, aes17-1991, and the electronic industries association of japan, eiaj cp-307. total harmonic distortion + noise the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 20 hz to 20 khz), including distortion components. expressed in decibels. adcs are measured at -1dbfs as suggested in aes 17-1991 annex a. idle channel noise / signal-to-noise-ratio the ratio of the rms analog output level with 1 khz full scale digital input to the rms analog output level with all zeros into the digital input. measured a-weighted over a 10 hz to 20 khz bandwidth. units in decibels. this specification has been standardized by the audio engineering society, aes17-1991, and referred to as idle channel noise. this specification has also been standardized by the electronic industries association of japan, eiaj cp-307, and referred to as signal-to-noise-ratio. total harmonic distortion (thd) thd is the ratio of the test signal amplitude to the rms sum of all the in-band harmonics of the test signal. units in decibels. interchannel isolation a measure of crosstalk between channels. measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. units in decibels. frequency response a measure of the amplitude response variation from 20hz to 20 khz relative to the amplitude response at 1 khz. units in decibels. interchannel gain mismatch for the adcs, the difference in input voltage that generates the full scale code for each channel. for the dacs, the difference in output voltages for each channel with a full scale digital input. units are in decibels. gain error the deviation from the nominal full scale output for a full scale input. gain drift the change in gain value with temperature. units in ppm/c. offset error for the adcs, the deviation in lsbs of the output from mid-scale with the selected input grounded. for the dacs, the deviation of the output from zero (relative to cmout) with mid- scale input code. units are in volts.
cs4228 ds307pp1 29 package dimensions notes: 1. d and e1 are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. dimension b does not include dambar protrusion/intrusion. allowable dambar protrusion shall be 0.13 mm total in excess of b dimension at maximum material condition. dambar intrusion shall not reduce dimension b by more than 0.07 mm at least material condition. 3. these dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. inches millimeters note dim min max min max a -- 0.084 -- 2.13 a1 0.002 0.010 0.05 0.25 a2 0.064 0.074 1.62 1.88 b 0.009 0.015 0.22 0.38 2,3 d 0.390 0.413 9.90 10.50 1 e 0.291 0.323 7.40 8.20 e1 0.197 0.220 5.00 5.60 1 e 0.022 0.030 0.55 0.75 l 0.025 0.041 0.63 1.03 0 8 0 8 28l ssop package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view

▲Up To Search▲

Price & Availability of CS4228-KS

	To Download CS4228-KS Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .